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? 2016 microchip technology inc. ds00002264a-page 1 features ? single-chip 10base-t/1 00base-tx ieee 802.3 compliant ethernet transceiver ? mii interface support ? back-to-back mode support for a 100 mbps cop- per repeater ? mdc/mdio management interface for phy reg- ister configuration ? programmable interrupt output ? led outputs for link and activity status indica- tion ? on-chip termination resistors for the differential pairs ? baseline wander correction ? hp auto mdi/mdi-x to reliably detect and cor- rect straight-through and crossover cable con- nections with disable and enable option ? auto-negotiation to automatically select the highest link-up speed (10/100 mbps) and duplex (half/full) ? power-down and power-saving modes ? linkmd ? tdr-based cable diagnostics to iden- tify faulty copper cabling ? parametric nand tree support for fault detec- tion between chip i/os and the board ? hbm esd rating (6 kv) ? loopback modes for diagnostics ? single 3.3v power supply with v dd i/o options for 1.8v, 2.5v, or 3.3v ? built-in 1.2v regulator for core ? available in 48-pin 7 mm x 7 mm lqfp package target applications ? game consoles ? ip phones ? ip set-top boxes ?ip tvs ?lom ? printers ksz8081mlx 10base-t/100base-tx physical layer transceiver
ksz8081mlx ds00002264a-page 2 ? 2016 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regarding this publication, please contact the marketing co mmunications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data s heet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and recommended workarounds, may exist for cur- rent devices. as device/doc umentation issues become known to us, we will publish an errata s heet. the errata will specify the revision of silicon and revision of document to which it applies. to determine if an errata sheet exis ts for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include -literature number) yo u are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2016 microchip technology inc. ds00002264a-page 3 ksz8081mlx table of contents 1.0 introduction .............................................................................................................. ....................................................................... 4 2.0 pin description and configuration ......................................................................................... ......................................................... 5 3.0 functional description .................................................................................................... .............................................................. 11 4.0 register descriptions ..................................................................................................... ............................................................... 26 5.0 operational charac teristics ............................................................................................... ............................................................ 35 6.0 electrical characteristics ................................................................................................ ............................................................... 36 7.0 timing diagrams ........................................................................................................... ................................................................ 38 8.0 reset circuit ............................................................................................................. .................................................................... 46 9.0 reference circuits ? le d strap-in pins .................................................................................... .................................................. 47 10.0 reference clock - connection and selection ............................................................................... .............................................. 48 11.0 magnetic - connection and selection ...................................................................................... ................................................... 49 12.0 package outline .......................................................................................................... ................................................................ 51 appendix a: data sheet revision history ....................................................................................... .................................................... 52 the microchip web site ........................................................................................................ .............................................................. 53 customer change notification service .......................................................................................... ..................................................... 53 customer support .............................................................................................................. ................................................................. 53 product identification system ................................................................................................. ............................................................ 54
ksz8081mlx ds00002264a-page 4 ? 2016 microchip technology inc. 1.0 introduction 1.1 general description the ksz8081mlx is a single-supply 10 base-t/100base-tx ethernet physical-laye r transceiver for transmission and reception of data over standard cat-5 unshielded twisted pair (utp) cable. the ksz8081mlx is a highly-integrated, comp act solution. it reduces board cost an d simplifies board layout by using on-chip termination resistors for the differential pairs, by integrating a low-noise regulator to supply the 1.2v core, and by offering 1.8/2.5/3.3v di gital i/o interface support. the ksz8081mlx offers the media independent interface (mii) for direct connection with mii-compliant ethernet mac processors and switches. the ksz8081mlx provides diagnostic feat ures to facilitate system bring-up and debugging in production testing and in product deployment. parametric nand tree support enables fault detection between ksz8081mlx i/os and the board. linkmd ? tdr-based cable diagnostics ident ify faulty copper cabling. the ksz8081mlx is available in the 48-pin, lead-free lqfp package. figure 1-1: system block diagram ksz8081mlx magnetics rj-45 connector media types: 10base-t 100base-tx on-chip termination resistors mii mdc/mdio management xo xi 25mhz xtal 22pf 22pf 10/100mbps mii mac
? 2016 microchip technology inc. ds00002264a-page 5 ksz8081mlx 2.0 pin description and configuration figure 2-1: 48-pin 7 mm x 7 mm lqfp assignment (top view) 1 nc nc txc rst# intrp / nand_tree# rext gnd rxer / iso gnd vdd_1.2 gnd gnd gnd gnd xo nc nc txd1 txd0 txen led1 / speed led0 / nwayen crs / config1 nc 2 3 8 13 14 16 17 29 30 31 32 33 34 35 36 41 42 43 44 45 46 47 48 rxp txm rxm 9 10 11 gnd 24 txd3 txd2 gnd col / config0 37 38 39 40 rxc / b-cast_off vddio nc rxdv / config2 25 26 27 28 rxd2 / phyad1 rxd1 / phyad2 rxd0 / duplex 21 22 23 mdio mdc rxd3 / phyad0 18 19 20 xi 15 txp 12 vdd_1.2 nc 4 5 nc vdda_3.3 6 7 ksz8081mlx
ksz8081mlx ds00002264a-page 6 ? 2016 microchip technology inc. table 2-1: signals - ksz8081mlx pin number pin name type note 2-1 description 1 gnd gnd ground. 2 gnd gnd ground. 3gndgnd ground. 4 vdd_!.2 p 1.2v core v dd (power supplied by ksz8081mlx ). decouple with 2.2 f and 0.1 f capacitors to ground, and join with pin 31 by power trace or plane. 5nc? no connect. this pin is not bonded and can be left floating. 6nc? no connect. this pin is not bonded and can be left floating. 7 vdda_3.3 p 3.3v analog v dd . 8 nc ? no connect. this pin is not bonded and can be left floating. 9 rxm i/o physical receive or transmit signal (? differential). 10 rxp i/o physical receive or transmit signal (+ differential). 11 txm i/o physical transmit or receive signal (? differential). 12 txp i/o physical transmit or receive signal (+ differential). 13 gnd gnd ground. 14 xo o crystal feedback for 25 mhz crystal. this pin is a no connect if an oscillator or external clock source is used. 15 xi i crystal/oscillator/external clock input (25 mhz 50 ppm). 16 rext i set phy transmit output current. connect a 6.49 k ? resistor to ground on this pin. 17 gnd gnd ground. 18 mdio ipu/ opu management interface (mii) data i/o. this pin has a weak pull-up, is open- drain, and requires an external 1.0 k ? pull-up resistor. 19 mdc ipu management interface (mii) clock input. this clock pin is synchronous to the mdio data pin. 20 rxd3/ phyad0 ipu/o mii mode: mii receive data output[3] ( note 2-2 ) config. mode: the pull-up/pull-down va lue is latched as phyaddr[0] at the de-assertion of reset. see the strap-in options - ksz8081mlx section for details. 21 rxd2/ phyad1 ipd/o mii mode: mii receive data output[2] ( note 2-2 ) config. mode: the pull-up/pull-down va lue is latched as phyaddr[1] at the de-assertion of reset. see the strap-in options - ksz8081mlx section for details. 22 rxd1/ phyad2 ipd/o mii mode: mii receive data output[1] ( note 2-2 ) config. mode: the pull-up/pull-down va lue is latched as phyaddr[2] at the de-assertion of reset. see the strap-in options - ksz8081mlx section for details.
? 2016 microchip technology inc. ds00002264a-page 7 ksz8081mlx 23 rxd0/ duplex ipu/o mii mode: mii receiv e data output[0] ( note 2-2 ) config. mode: the pull-up/pull-down value is latched as duplex at the de- assertion of reset. see the strap-in options - ksz8081mlx section for details. 24 gnd gnd ground. 25 vddio p 3.3v, 2.5v, or 1.8v digital v dd . 26 nc ? no connect. this pin is not bonded and can be left floating. 27 rxdv/ config2 ipd/o mii mode: mii receive data valid output. config. mode: the pull-up/pull-down va lue is latched as config2 at the de- assertion of reset. see the strap-in options - ksz8081mlx section for details. 28 rxc/ b-cast_off ipd/o mii mode: mii receive clock output. config. mode: the pull-up/pull-down value is latched as b-cast_off at the de-assertion of reset. see the strap-in options - ksz8081mlx section for details. 29 rxer/ iso ipd/o mii mode: mii receive error output config. mode: the pull-up/pull-down value is latched as isolate at thede- assertion of reset see the strap-in options - ksz8081mlx section for details. 30 gnd gnd ground. 31 vdd_1.2 p 1.2v core v dd (power supplied by ksz8081m lx). decouple with 0.1 f capacitor to ground, and join with pin 4 by power trace or plane. 32 intrp/ nand_tree# ipu/ opu interrupt output: programmable interrupt output. this pin has a weak pull-up, is open drain, and requires an external 1.0 k ? pull-up resistor. config. mode: the pull-up/pull-down va lue is latched as nand tree# at the de-assertion of reset. see the strap-in options - ksz8081mlx section for details. 33 txc ipd/o mii mode: mii transmit clock output. at the de-assertion of reset, this pin needs to latch in a pull-down value for normal operation. if mac side pulls this pin high, see register 16h, bit [15] for solu- tion. it is better having an external pull-down resistor to avoid mac side pulls this pin high. 34 txen i mii mode: mii transmit enable input. 35 txd0 i mii mode: mii transmit data input[0] ( note 2-3 ) 36 txd1 i mii mode: mii transmit data input[1] ( note 2-3 ) 37 gnd gnd ground. 38 txd2 i mii mode: mii transmit data input[2] ( note 2-3 ) 39 txd3 i mii mode: mii transmit data input[3] ( note 2-3 ) table 2-1: signals - ksz8081mlx (continued) pin number pin name type note 2-1 description
ksz8081mlx ds00002264a-page 8 ? 2016 microchip technology inc. 40 col/ config0 ipd/o mii mode: mii collision detect output config. mode: the pull-up/pull-down va lue is latched as config0 at the de- assertion of reset. see the strap-in options - ksz8081mlx section for details. 41 crs/ config1 ipd/o mii mode: mii carrier sense output config. mode: the pull-up/pull-down va lue is latched as config1 at the de- assertion of reset. see the strap-in options - ksz8081mlx section for details. 42 led0/ nwayen ipu/o led output: progra mmable led0 output config. mode: latched as auto-negotiat ion enable (register 0h, bit [12]) at the de-assertion of reset. see the strap-in options section for details. the led0 pin is programmable using register 1fh bits [5:4], and is defined as follows: led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definition no link high off link low on led mode = [10], [11] reserved 43 led1/ speed ipu/o led output: programmable led1 output config. mode: latched as speed (register 0h, bit [13]) at the de-assertion of reset. see the strap-in options section for details. the led1 pin is programmable using register 1fh bits [5:4], and is defined as follows: led mode = [00] speed pin state led definition 10base-t high off 100base-tx low on led mode = [01] activity pin state led definition no activity high off activity toggle blinking led mode = [10], [11] reserved table 2-1: signals - ksz8081mlx (continued) pin number pin name type note 2-1 description
? 2016 microchip technology inc. ds00002264a-page 9 ksz8081mlx note 2-1 p = power supply gnd = ground i = input o = output i/o = bi-directional ipu = input with internal pull-up (see electrical characteristics for value). ipu/o = input with in ternal pull-up (see electrical characteristics for value) duri ng power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipu/opu = input with internal pull-up (see electrical characteristics for value) and output with internal pull-up (see electrical characteristics for value). note 2-2 mii rx mode: the rxd[3: 0] bits are synchronous with rxc. when rxdv is asserted, rxd[3:0] presents valid data to the mac. note 2-3 mii tx mode: the txd[3:0] bits are synchronous with txc. when txen is asserted, txd[3:0] presents valid data from the mac. 2.1 strap-in options the phyad[1:0] strap-in pin is latched at th e de-assertion of reset. in some syst ems, the rmii mac receive input pins may drive high/low during power-up or reset, and consequently cause the phyad[1:0] strap-in pin, a shared pin with the rmii crs_dv signal, to be latched to the unintended hi gh/low state. in this case an external pull-up (4.7 k ? ) or pull- down (1.0 k ? ) should be added on the phyad[1:0] strap-in pin to ensure that the intended val ue is strapped-in correctly. 44 test/nc ipd no connect for normal operation, an external pull-up resistor for nand tree testing. 45 nc ? no connect. this pin is not bonded and can be left floating. 46 nc ? no connect. this pin is not bonded and can be left floating. 47 rst# ipu chip reset (active low). 48 nc ? no connect. this pin is not bonded and can be left floating. table 2-2: strap-in options - ksz8081mlx pin number pin name type note 2-4 description 22 phyad2 ipd/o the phy address is latched at de-assertion of reset and is configu- rable to any value from 0 to 7. the default phy address is 00001. phy address 00000 is enabled only if the b-cast_off strap-in pin is pulled high. phy address bits [4:3] are set to 00 by default. 21 phyad1 20 phyad0 27 config2 ipd/o the config[2:0] strap-in pins are latched at the de-assertion of reset. 41 config1 config[2:0] mode 000 mii (default) 40 config0 110 mii back-to-back 001 ? 101, 111 reserved, not used table 2-1: signals - ksz8081mlx (continued) pin number pin name type note 2-1 description
ksz8081mlx ds00002264a-page 10 ? 2016 microchip technology inc. note 2-4 ipu/o = input with internal pull-up (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipd/o = input with internal pull-down (see electrical characteristics for value) during power-up/reset; output pin otherwise. ipu/opu = input with internal pull-up (see electrical characteristics for value) and output with internal pull-up (see electrical characteristics for value). 29 iso ipd/o isolate mode: pull-up = enable pull-down (default) = disable at the de-assertion of reset, this pin value is latched into register 0h, bit [10]. 43 speed ipu/o speed mode: pull-up (default) = 100 mbps pull-down = 10 mbps at the de-assertion of reset, this pin value is latched into register 0h, bit [13] as the speed select, and also is latched into register 4h (auto-negotiation advertisement) as the speed capability support. 23 duplex ipu/o duplex mode: pull-up (default) = half-duplex pull-down = full-duplex at the de-assertion of reset, this pin value is latched into register 0h, bit [8]. 42 nwayen ipu/o nway auto-negotiation enable: pull-up (default) = enable auto-negotiation pull-down = disable auto-negotiation at the de-assertion of reset, this pin value is latched into register 0h, bit [12]. 28 b-cast_off ipd/o broadcast off ? for phy address 0: pull-up = phy address 0 is set as an unique phy address pull-down (default) = phy address 0 is set as a broadcast phy address at the de-assertion of reset, this pin value is latched by the chip. 32 nand_tree# ipu/opu nand tree mode: pull-up (default) = disable pull-down = enable at the de-assertion of reset, this pin value is latched by the chip. table 2-2: strap-in options - ksz8081mlx (continued) pin number pin name type note 2-4 description
? 2016 microchip technology inc. ds00002264a-page 11 ksz8081mlx 3.0 functional description the ksz8081mlx is an integrated single 3. 3v supply fast ethernet transceiver. it is fully compliant with the ieee 802.3 specification, and reduces board cost and simplifies board layout by usin g on-chip termination resistors for the two dif- ferential pairs and by integrating the regulator to supply the 1.2v core. on the copper media side, the ksz8081mlx supports 10 base-t and 100base-tx for transmission and reception of data over a standard cat-5 unshielded twisted pair (utp) cabl e, and hp auto mdi/mdi-x for reliable detection of and correction for straight-through and crossover cables. on the mac processor side, the ksz8081mlx offers the m edia independent interface (mii) for direct connection with mii compliant ethernet mac processors and switches. the mii management bus option gives the mac processor complete access to the ksz8081mlx control and status registers. additionally, an interrupt pin eliminates t he need for the processor to poll for phy status change. 3.1 10base-t/100base-tx transceiver 3.1.1 100base-tx transmit the 100base-tx transmit function performs parallel-to-s erial conversion, 4b/5b encoding, scrambling, nrz-to-nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, wh ich converts the mii data from the mac into a 125 mhz serial bit stream. the data and control stream is then converted into 4b/5b coding and followed by a scrambler. the serialized data is further converted from nrz-to- nrzi format, and then transmitted in mlt3 current output. the output current is set by an external 6.49 k ? 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4 ns and complies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timi ng jitter. the wave-shaped 10ba se-t output is also incorp orated into the 100base-tx transmitter. 3.1.2 100base-tx receive the 100base-tx receiver function performs adaptive equalization, dc restoration, mlt3-to-nrz i conversion, data and clock recovery, nrzi-to-nrz conversi on, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalization filter to com pensate for inter-symbol interfer ence (isi) over the twisted pair cable. because the amplitude loss a nd phase distortion is a function of the cable length, the equ alizer must adjust its characteristics to optimize performanc e. in this design, the variable equaliz er makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, then t unes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc-restoration and data-conversion block. the dc-restoration circuit com- pensates for the effect of baseline wander and improves the dynamic range. the differential data-conversion circuit con- verts mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock-recovery circuit extracts the 125 mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into nrz format. this signal is sent through the de-scrambler, then the 4b/5b decoder. finally, the nrz serial data is converted to mii format and provided as the input data to the mac. 3.1.3 scrambler/de-scrambler (100base-tx only) the scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (emi) and baseline wander. the de-scrambler recovers the scrambled signal. 3.1.4 10base-t transmit the 10base-t drivers are incor porated with the 100base-tx dr ivers to allow for transmi ssion using the same mag- netic. the drivers perform internal wa ve-shaping and pre-emphasis, and output 10base-t signa ls with typical ampli- tude of 2.5v peak. the 10base-t signa ls have harmonic contents that are at least 27 db below the fundamental frequency when driven by an all-ones manchester-encoded signal. 3.1.5 10base-t receive on the receive side, input buffer and level detecting squelch ci rcuits are used. a differential input receiver circuit and a phase-locked loop (pll) performs the decoding function. t he manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400 mv, or with short pulse widths, to prevent
ksz8081mlx ds00002264a-page 12 ? 2016 microchip technology inc. noise at the rxp and rxm inputs from falsely triggering t he decoder. when the input exce eds the squelch limit, the pll locks onto the incoming signal and the ksz8 081mlx decodes a data fr ame. the receive clock is kept active during idle periods between data receptions. 3.1.6 sqe and jabber function (10base-t only) in 10base-t operation, a short pulse is put out on the col pin after each frame is transmitted. this sqe test is needed to test the 10base-t transmit/receive path. if transmit e nable (txen) is high for more than 20 ms (jabbering), the 10base-t transmitter is disabled and co l is asserted high. if txen is th en driven low for more than 250 ms, the 10base-t transmitter is re-enabled and col is de-asserted (returns to low). 3.1.7 pll clock synthesizer the ksz8081mlx gener ates all internal clo cks and all external clocks for system timing from an external 25 mhz crys- tal, oscillator, or reference clock. 3.1.8 auto-negotiation the ksz8081mlx conforms to the auto-negotiation pr otocol, defined in clause 28 of the ieee 802.3 specification. auto-negotiation allows unshielded twisted pair (utp) link partners to select the highest common mode of operation. during auto-negotiation, link partners advertise capabilities across the utp link to each other and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex opera tion mode from highest to lowest priority. ? priority 1: 100base-tx, full-duplex ? priority 2: 100base-tx, half-duplex ? priority 3: 10base-t, full-duplex ? priority 4: 10base-t, half-duplex if auto-negotiation is not supported or the ksz8081mlx link partner is forc ed to bypass auto-negotiation, then the ksz8081mlx sets its operating mode by observing the signal at its receiver. this is known as parallel detection, and allows the ksz8081mlx to establish a li nk by listening for a fixed signal protocol in the absence of the auto-negotiation advertisement protocol. auto-negotiation is enabled by either hardware pin strapping (nwayen, pin 42) or software (register 0h, bit [12]). by default, auto-negotiation is enabled after power-up or har dware reset. after that, auto-negotiation can be enabled or disabled by register 0h, bit [12]. if auto-negotiation is disa bled, the speed is set by register 0h, bit [13], and the duplex is set by register 0h, bit [8]. the auto-negotiation link-up process is shown in figure 3-1 .
? 2016 microchip technology inc. ds00002264a-page 13 ksz8081mlx figure 3-1: auto-ne gotiation flow chart 3.2 mii interface the media independent interface (mii) is compliant with th e ieee 802.3 specification. it provides a common interface between mii phys and macs, and has the following key characteristics: ? pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indi- cation). ? 10 mbps and 100 mbps data rates are supported at both half- and full-duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 4 bits wide, a nibble. by default, the ksz8081mlx is configured to mii mode afte r it is powered up or hardware reset with the following: ? a 25 mhz crystal connected to xi, xo (pins 15, 14), or an external 25 mhz clock source (oscillator) connected to xi. ? the config[2:0] strapping pins (pins 27, 41, 40) set to 000 (default setting). 3.2.1 mii signal definition table 3-1 describes the mii signals. refer to clause 22 of the ieee 802.3 spec ification for detailed information. start auto-negotiation force link setting listen for 10base-t link pulses listen for 100base-tx idles attempt auto- negotiation link mode set bypass auto- negotiation and set link mode link mode set? parallel operation no yes yes no join flow
ksz8081mlx ds00002264a-page 14 ? 2016 microchip technology inc. 3.2.1.1 transmit clock (txc) txc is sourced by the phy. it is a continuous clock th at provides the timing reference for txen and txd[3:0]. txc is 2.5 mhz for 10 mbps operation and 25 mhz for 100 mbps operation. 3.2.1.2 transmit enable (txen) txen indicates that the mac is presenting nibbles on txd[ 3:0] for transmission. it is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the mii. it is negated before the first txc followin g the final nibble of a frame. txen transitions synchronou sly with respect to txc. 3.2.1.3 transmit data[3:0] (txd[3:0]) when txen is asserted, txd[3: 0] are the data nibbles accepted by the phy for transmission. txd[3:0] is 00 to indicate idle when txen is de-asserted. txd[3:0] transitions synchro nously with respect to txc. 3.2.1.4 receive clock (rxc) rxc provides the timing referenc e for rxdv, rxd[3:0], and rxer. in 10 mbps mode, rxc is recovered from the line while the ca rrier is active. rxc is derived from the phy?s reference clock when the line is idle or the link is down. in 100 mbps mode, rxc is continuously recovered from the line. if the link is down, rx c is derived from the phy?s reference clock. rxc is 2.5 mhz for 10 mbps operation and 25 mhz for 100 mbps operation. 3.2.1.5 receive data valid (rxdv) rxdv is driven by the phy to indicate that the phy is presenting recovered and decoded nibbles on rxd[3:0]. in 10 mbps mode, rxdv is asserted with the first nibble of the start-of-frame delimiter (s fd), 5d, and remains asserted until the end of the frame. in 100 mbps mode, rxdv is asserted from the first ni bble of the preamble to th e last nibble of the frame. rxdv transitions synchronously with respect to rxc. 3.2.1.6 receive data[3:0] (rxd[3:0]) rxd[3:0] transitions synchronously with respect to rxc. for each clock period in which rxdv is asserted, rxd[3:0] transfers a nibble of recovered data from the phy. table 3-1: mii signal definition mii signal name direction with respect to phy, ksz8081 signal direction with respect to mac description txc output input transmit clock (2.5 mhz for 10 mbps; 25 mhz for 100 mbps) txen input output transmit enable txd[3:0] input output transmit data[3:0] rxc output input receive clock (2.5 mhz for 10 mbps; 25 mhz for 100 mbps) rxdv output input receive data valid rxd[3:0] output input receive data[3:0] rxer output input or not required receive error crs output input carrier sense col output input collision detection
? 2016 microchip technology inc. ds00002264a-page 15 ksz8081mlx 3.2.1.7 receive error (rxer) rxer is asserted for one or more rxc periods to indicate that a symbol error (for exampl e, a coding error that a phy can detect that may otherwise be undetectable by the mac sub-layer) was detected somewhere in the frame being transferred from the phy. rxer transitions synchronously with respect to rxc. 3.2.1.8 carrier sense (crs) crs is asserted and de-asserted as follows: in 10 mbps mode, crs assertion is based on the reception of valid preambles. crs de-asse rtion is based on the recep- tion of an end-of-frame (eof) marker. in 100 mbps mode, crs is asserted when a start-of-stream delim iter or /j/k symbol pair is detected. crs is de-asserted when an end-of-stream delimiter or /t/r symbol pair is detected. additionally, the pma layer de-asserts crs if idle symbols are received without /t/r. 3.2.1.9 collision detection (col) col is asserted in half-duplex mode whenever the transmit ter and receiver are simultaneously active on the line. this informs the mac that a collision has occurred during its transmission to the phy. col transitions asynchronously with respect to txc and rxc. 3.2.2 mii signal diagram the ksz8081mlx mii pin connections to the mac are shown in figure 3-2 . figure 3-2: ksz8081mlx mii interface ' ksz8081mlx txc txen txd[3 :0] rxc rxdv rxd[3 :0] txc txen txd[3:0 ] rxc rxdv rxd[3:0] mii ethernet mac rxer rxer crs crs col col
ksz8081mlx ds00002264a-page 16 ? 2016 microchip technology inc. 3.3 back-to-back mode ? 100 mbps copper repeater two ksz8081mlx devices can be connected back-to-back to form a 100base-tx to 100base-tx copper repeater. 3.3.1 mii back-to-back mode in mii back-to-back mode, a ksz8081mlx interfaces with another ksz8081mlx to provide a complete 100 mbps cop- per repeater solution. the ksz8081mlx devices are configured to mii back-to -back mode after power-up or reset with the following: ? strapping pin config[2:0] (p ins 27, 41, 40) set to 110. ? a common 25 mhz reference clock connected to xi (pin 15) of both ksz8081mlx devices. ? mii signals connected as shown in table 3-2 . figure 3-3: ksz8081mlx to ksz8081mlx back-to -back copper repeater table 3-2: mii signal connection for mi i back-to-back mode (100base-tx copper repeater) ksz8081mlx (100base-tx copper) [device 1] ksz8081mlx (100base-tx copper) [device 2] pin name pin number pin type pin name pin number pin type rxdv 27 output txen 34 input rxd3 20 output txd3 39 input rxd2 21 output txd2 38 input rxd1 22 output txd1 36 input rxd0 23 output txd0 35 input txen 34 input rxdv 27 output txd3 39 input rxd3 20 output txd2 38 input rxd2 21 output txd1 36 input rxd1 22 output txd0 35 input rxd0 23 output ksz8081m lx (copper mode) ksz8081mlx osc xi xi 25mhz (copper mode) rxp/rxm rxp/rxm txp/txm txp/txm txd txd rxd rxd
? 2016 microchip technology inc. ds00002264a-page 17 ksz8081mlx 3.4 mii management (miim) interface the ksz8081mlx supports the ieee 802. 3 mii management interface, also kn own as the management data input/ output (mdio) interface. this interface allows an upper-lay er device, such as a mac proc essor, to monitor and control the state of the ksz8081mlx. an external device with miim capability is used to read the phy status and/or configure the phy settings. more details about the miim interface c an be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates th e clock line (mdc) and the data line (mdio). ? a specific protocol that o perates across the physical connection mentioned earlier, which allows the external con- troller to communicate with one or more phy devices. ? a set of 16-bit mdio registers. registers [0:8] are st andard registers, and their func tions are defined in the ieee 802.3 specification. the additional regi sters are provided for expanded functionality. see the register map section for details. as the default, the ksz8081mlx supports unique phy addresses 1 to 7, and broadcast phy address 0. the latter is defined in the ieee 802.3 specif ication, and can be used to read/write to a single ksz8081mlx device, or write to mul- tiple ksz8081mlx devices simultaneously. phy address 0 can optionally be disabled as the broadcas t address by either hardware pin strapping (b-cast_off, pin 28) or software (register 16h, bit [9]), and assigned as a unique phy address. the phyad[2:0] strapping pins are used to assign a unique phy address between 0 and 7 to each ksz8081mlx device. the miim interface can operates up to a maximum clock speed of 10 mhz mac clock. table 3-3 shows the mii management frame format for the ksz8081mlx. 3.5 interrupt (intrp) intrp (pin 32) is an optional interrupt sign al that is used to inform the external controller that there has been a status update to the ksz8081mlx phy register. bits [15:8] of regist er 1bh are the interrupt control bits to enable and disable the conditions for asserting the intrp signal. bits [7:0] of re gister 1bh are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt st atus bits are cleared after reading register 1bh. bit [9] of register 1fh sets the interrupt level to active high or active low. the default is active low. the mii management bus option gives the mac processor complete access to the ksz8081mlx control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll the phy for status change. 3.6 hp auto mdi/mdi-x hp auto mdi/mdi-x configuration elimi nates the need to decide whether to use a straight cable or a crossover cable between the ksz8081mlx and its link partner. this feature a llows the ksz8081mlx to use either type of cable to con- nect with a link partner that is in either mdi or mdi-x mo de. the auto-sense function detects transmit and receive pairs from the link partner and assigns transmit and receive pairs of the ksz8081mlx accordingly. hp auto mdi/mdi-x is enabled by default. it is disabled by writing a ?1? to register 1fh, bit [13]. mdi and mdi-x mode is selected by register 1fh, bit [14] if hp auto mdi/mdi-x is disabled. an isolation transformer with symmetrical transmit and rece ive data paths is recommended to support auto mdi/mdi-x. table 3-4 shows how the ieee 802.3 standard defines mdi and mdi-x. table 3-3: mii management fram e format for the ksz8081mlx preamble start of frame read/ write op code phy address bits[4:0] reg address bits[4:0] ta data bits[15:0] idle read 32 1?s 01 10 000aa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 000aa rrrrr 10 dddddddd_dddddddd z
ksz8081mlx ds00002264a-page 18 ? 2016 microchip technology inc. 3.6.1 straight cable a straight cable connects an mdi device to an mdi-x device, or an mdi-x device to an mdi device. figure 3-4 shows a typical straight cable connection between a nic card (mdi device) and a switch or hub (mdi-x device). 3.6.2 crossover cable a crossover cable connects an mdi device to another mdi device, or an mdi-x device to another mdi-x device. figure 3-5 shows a typical crossover cable connection between two switches or hubs (two mdi-x devices). table 3-4: mdi/mdi-x pin description mdi mdi-x rj-45 pin signal rj-45 pin signal 1 tx+ 1 rx+ 2tx?2rx? 3 rx+ 3 tx+ 6 rx? 6 tx? figure 3-4: typical straight cable connection receive pair transmit pair receive pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair modular connector (rj-45) nic straight cable 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch)
? 2016 microchip technology inc. ds00002264a-page 19 ksz8081mlx 3.7 loopback mode the ksz8081mlx supports the following loopback operat ions to verify analog and/or digital data paths. ? local (digital) loopback ? remote (analog) loopback 3.7.1 local (dig ital) loopback this loopback mode checks the mii transmit and receive data paths between the ksz8081mlx and the external mac, and is supported for both speeds (10/100 mbps) at full-duplex. the loopback data path is shown in figure 3-6 . 1. the mii mac transmits frames to the ksz8081mlx. 2. frames are wrapped around inside the ksz8081mlx. 3. the ksz8081mlx transmits frames back to the mii mac. figure 3-5: typical crossover cable connection figure 3-6: local (digital) loopback receive pair receive pair transmit pair 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 transmit pair 10/100 ethernet media dependent interface 10/100 ethernet media dependent interface modular connector (rj-45) hub (repeater or switch) crossover cable modular connector (rj-45) hub (repeater or switch) mii mac mii pcs (digital) afe (analog) ksz8081mlx
ksz8081mlx ds00002264a-page 20 ? 2016 microchip technology inc. the following programming action and register settings are used for local loopback mode: for 10/100 mbps loopback: set register 0h, bit [14] = 1 // enable local loopback mode bit [13] = 0/1 // select 10 mbps/100 mbps speed bit [12] = 0 // disable auto-negotiation bit [8] = 1 // select full-duplex mode 3.7.2 remote (analog) loopback this loopback mode checks the line (differential pairs, tran sformer, rj-45 connector, et hernet cable) transmit and receive data paths between the ksz8081mlx and its link partner, and is supported for 100base-tx full-duplex mode only. the loopback data path is shown in figure 3-7 . 1. the fast ethernet (100base-tx) phy link partner tran smits frames to the ksz8081mlx. 2. frames are wrapped around inside the ksz8081mlx. 3. the ksz8081mlx transmits frames back to th e fast ethernet (100base-tx) phy link partner. the following programming steps and register settings are used for remote loopback mode: 1. set register 0h, bits [13] = 1 // select 100 mbps speed bit [12] = 0 // disable auto-negotiation bit [8] = 1 // select full-duplex mode or just auto-negotiate and li nk up at 100base-tx full-duplex mode with the link partner. 2. set register 1fh, bit [2] = 1 // enable remote loopback mode figure 3-7: remote (analog) loopback rj-45 rj-45 cat-5 (utp) ksz8081mlx 100base-tx link partner afe (analog) pcs (digital) mii
? 2016 microchip technology inc. ds00002264a-page 21 ksz8081mlx 3.8 linkmd ? cable diagnostic the linkmd function uses time-domain reflectometry (tdr) to analyze the cabling plant for common cabling problems. these include open circuits, short circuits, and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi or mdi-x pair, then analyzing the shape of the reflected signal to determine the type of fault. the time duration for the reflected signal to return provides the approximate distance to the cabling fault. the linkmd function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd is initiated by accessing register 1dh, the linkmd c ontrol/status register, in conjun ction with register 1fh, the phy control 2 register. the latter register is used to disable auto mdi/mdi-x and to select either mdi or mdi-x as the cable differential pair for testing. 3.8.1 usage the following is a sample procedure for using linkmd with registers 1dh and 1fh: 1. disable auto mdi/mdi-x by writing a ?1? to register 1fh, bit [13]. 2. start cable diagnostic test by writing a ?1? to regist er 1dh, bit [15]. this enable bit is self-clearing. 3. wait (poll) for register 1dh, bit [15] to return a ?0?, and indicating cable diagnostic test is completed. 4. read cable diagnostic test results in register 1dh, bits [14:13]. the results are as follows: 00 = normal condition (valid test) 01 = open condition detected in cable (valid test) 10 = short condition detected in cable (valid test) 11 = cable diagnostic test failed (invalid test) the ?11? case, invalid test, occurs when the device is unable to shut down the link partner. in this instance, the test is not run because it would be impossible for the device to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. get distance to fault by concatenati ng register 1dh, bits [8:0] and multiplying the result by a constant of 0.38. the distance to the cable fault can be determined by the following formula: equation 3-1: concatenated value of registers 1dh bits [8:0] shoul d be converted to decimal before multiplying by 0.38. the constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation that varies significantly from the norm. 3.9 nand tree support the ksz8081mlx provides parametric nand tree support fo r fault detection between chip i/os and board. the nand tree is a chain of nested nand gates in which each ksz8081mlx digital i/o (nand tree input) pin is an input to one nand gate along the chain. at the end of the chain, the crs/config1 pin prov ides the output for the nested nand gates. the nand tree test process includes: ? enabling nand tree mode ? pulling all nand tree input pins high ? driving each nand tree input pin low, sequentially, according to the nand tree pin order ? checking the nand tree output to make sure there is a toggle high-to-low or low-to-high for each nand tree input driven low table 3-5 lists the nand tree pin order. ddis ce tan to cable fault in meters ?? 0.38 register 1dh, bits[8:0] ?? ? =
ksz8081mlx ds00002264a-page 22 ? 2016 microchip technology inc. 3.9.1 nand tree i/o testing use the following procedure to check for faults on the ksz8081mlx digital i/o pin connections to the board: 1. enable nand tree mode using either a hardware strap-in pin (nand_tree#, pin 32) or software (register 16h, bit [5]). pin 44 test/nc has to use a pull-up resistor for normal nand tree testing. 2. use board logic to drive all ksz8081mlx nand tree input pins high. 3. use board logic to drive each nand tree input pin, in ksz8081mlx nand tree pin order, as follows: a) toggle the first pin (mdio) from high to low, and verify that the crs/config1 pin sw itches from high to low to indicate that the first pin is connected properly. b) leave the first pin (mdio) low. c) toggle the second pin (mdc) from high to low, and verify that the crs/config1 pin switches from low to high to indicate that the second pin is connected properly. d) leave the first pin (mdio) and the second pin (mdc) low. e) toggle the third pin from high to low, and verify that the crs/config1 pin switches from high-to-low to indi- cate that the third pin is connected properly. f) continue with this sequence until all ksz8081m lx nand tree input pins have been toggled. each ksz8081mlx nand tree input pin mu st cause the crs/config1 output pin to toggle high-to-low or low-to-high to indicate a good connection. if the crs pin fails to togg le when the ksz8081mlx input pin toggles from high to low, the input pin has a fault. 3.10 power management the ksz8081mlx incorporates a number of power-management modes and features that pr ovide methods to consume less energy. these are discussed in the following sections. 3.10.1 power-saving mode power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. it is enabled by writing a ?1? to register 1fh, bit [10], and is in effect when auto-negotiation mode is enabled and the cable is discon- nected (no link). table 3-5: nand tree test pin order for ksz8081mlx pin number pin name nand tree description 18 mdio input 19 mdc input 20 rxd3 input 21 rxd2 input 22 rxd1 input 23 rxd0 input 27 rxdv input 28 rxc input 29 rxer input 32 intrp input 33 txc input 34 txen input 35 txd0 input 36 txd1 input 38 txd2 input 39 txd3 input 42 led0 input 43 led1 input 40 col input 41 crs output
? 2016 microchip technology inc. ds00002264a-page 23 ksz8081mlx in this mode, t he ksz8081mlx shuts down all transce iver blocks, except for the trans mitter, energy detect, and pll circuits. by default, power-saving mode is disabled after power-up. 3.10.2 energy-detect power-down mode energy-detect power-down (edpd) mode is used to furthe r reduce transceiver power consumption when the cable is unplugged. it is enabled by writing a ?0? to register 18h, bit [11], and is in ef fect when auto-negotiation mode is enabled and the cable is disconnected (no link). edpd mode works with the pll off (set by writing a ?1? to r egister 10h, bit [4] to automatic ally turn the pll off in edpd mode) to turn off all ksz8081mlx transceiver blocks, ex cept for the transmitter and energy-detect circuits. power can be reduced further by extending the time interval between transmissions of link pulses to check for the pres- ence of a link partner. the periodic transmission of link pul ses is needed to ensure two link partners in the same low- power state, with auto mdi/mdi-x disabled, can wa ke up when the cable is connected between them. by default, energy-detect power-down mode is disabled after power-up. 3.10.3 power-down mode power-down mode is used to power down the ksz8081mlx devic e when it is not in use after power-up. it is enabled by writing a ?1? to register 0h, bit [11]. in this mode, the ksz8081mlx disables all internal func tions except the mii management interface. the ksz8081mlx exits (disables) power-down mode after register 0h, bit [11] is set back to ?0?. 3.10.4 slow-oscillator mode slow-oscillator mode is used to disconnect the input refer ence crystal/clock on xi (pin 15) and select the on-chip slow oscillator when the ksz8081mlx device is not in use after powe r-up. it is enabled by writing a ?1? to register 11h, bit [5]. slow-oscillator mode works in conjunction with power-down mode to put the ksz8081mlx device in the lowest power state with all internal functions disabled except the mii man agement interface. to properly exit this mode and return to normal phy operation, use the following programming sequence: 1. disable slow-oscillator mode by writing a ?0? to register 11h, bit [5]. 2. disable power-down mode by writing a ?0? to register 0h, bit [11]. 3. initiate software reset by writin g a ?1? to register 0h, bit [15].
ksz8081mlx ds00002264a-page 24 ? 2016 microchip technology inc. 3.11 reference circuit for power and ground connections the ksz8081mlx is a single 3.3v supply device with a built-i n regulator to supply the 1.2v core. the power and ground connections are shown in figure 3-8 and ta b l e 3 - 6 for 3.3v v ddio . 3.12 typical current/power consumption table 3-7 , table 3-8 , and ta b l e 3 - 9 show typical values for current consumption by the transceiver (vdda_3.3) and dig- ital i/o (vddio) power pins and typical values for pow er consumption by the ksz8081 mlx device for the indicated nominal operating voltages. these current and power consum ption values include the transmit driver current and on- chip regulator current for the 1.2v core. figure 3-8: ksz8081mlx po wer and ground connections table 3-6: ksz8081mlx power pin description power pin pin number description vdd_1.2 4 connect with pin 31 by power trace or plane. decouple with 2.2 f and 0.1 f capacitors to ground. vdda_3.3 7 connect to board?s 3.3v supply through a ferrite bead. decouple with 22 f and 0.1 f capacitors to ground. vddio 25 connect to board?s 3.3v supply for 3.3v v ddio . decouple with 22 f and 0.1 f capacitors to ground. vdd_1.2 31 connect with pin 4 by power trace or plane. decouple with 0.1 f capacitor to ground. table 3-7: typical current/power consum ption (vdda_3.3 = 3.3v, vddio = 3.3v) condition 3.3v transceiver (vdda_3.3) 3.3v digital i/os (vddio) total chip power 100base-tx link-up (no traffic) 34 ma 12 ma 152 mw 100base-tx full-duplex @ 100% utilization 34 ma 13 ma 155 mw 10base-t link-up (no traffic) 14 ma 11 ma 82.5 mw 10base-t full-duplex @ 100% utilization 30 ma 11 ma 135 mw vddio ksz8081mlx gnd 1 3.3v vdda_3.3 0.1f ` ` ` 4 31 vdd_1.2 vdd_1.2 7 ferrite bead 25 0.1uf ` 213 17 24 30 37 3 2.2f 0.1f 0.1f 22f 22f
? 2016 microchip technology inc. ds00002264a-page 25 ksz8081mlx power-saving mode (reg. 1fh, bit [10] = 1) 14 ma 10 ma 79.2 mw edpd mode (reg. 18h, bit [11] = 0) 10 ma 10 ma 66 mw edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.77 ma 1.54 ma 1.75 mw software power-down mode (reg. 0h, bit [11] =1) 2.59 ma 1.51 ma 13.5 mw software power-down mode (reg. 0h, bit [11] =1) and slow-oscillator mode (reg. 11h, bit [5] =1) 1.36 ma 0.45 ma 5.97 mw table 3-8: typical current/power consum ption (vdda_3.3 = 3.3v, vddio = 2.5v) condition 3.3v transceiver (vdda_3.3) 2.5v digital i/os (vddio) total chip power 100base-tx link-up (no traffic) 34 ma 11 ma 140 mw 100base-tx full-duplex @ 100% utilization 34 ma 12 ma 142 mw 10base-t link-up (no traffic) 15 ma 10 ma 74.5 mw 10base-t full-duplex @ 100% utilization 27 ma 10 ma 114 mw power-saving mode (reg. 1fh, bit [10] = 1) 15 ma 10 ma 74.5 mw edpd mode (reg. 18h, bit [11] = 0) 11 ma 10 ma 61.3 mw edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.55 ma 1.35 ma 15.1 mw software power-down mode (reg. 0h, bit [11] =1) 2.29 ma 1.34 ma 10.9 mw software power-down mode (reg. 0h, bit [11] =1) and slow-oscillator mode (reg. 11h, bit [5] =1) 1.15 ma 0.29 ma 4.52 mw table 3-9: typical current/power consum ption (vdda_3.3 = 3.3v, vddio = 1.8v) condition 3.3v transceiver (vdda_3.3) 1.8v digital i/os (vddio) total chip power 100base-tx link-up (no traffic) 34 ma 11 ma 132 mw 100base-tx full-duplex @ 100% utilization 34 ma 12 ma 134 mw 10base-t link-up (no traffic) 15 ma 9 ma 65.7 mw 10base-t full-duplex @ 100% utilization 27 ma 9 ma 105 mw power-saving mode (reg. 1fh, bit [10] = 1) 15 ma 9 ma 65.7 mw edpd mode (reg. 18h, bit [11] = 0) 11 ma 9 ma 52.5 mw edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 4.05 ma 1.21 ma 15.5 mw software power-down mode (reg. 0h, bit [11] =1) 2.79 ma 1.21 ma 11.4 mw software power-down mode (reg. 0h, bit [11] =1) and slow-oscillator mode (reg. 11h, bit [5] =1) 1.65 ma 0.19 ma 5.79 mw table 3-7: typical current/power consum ption (vdda_3.3 = 3.3v, vddio = 3.3v) condition 3.3v transceiver (vdda_3.3) 3.3v digital i/os (vddio) total chip power
ksz8081mlx ds00002264a-page 26 ? 2016 microchip technology inc. 4.0 register descriptions this chapter describes the various co ntrol and status registers (csrs). 4.1 register map 4.2 register descriptions table 4-1: registers supported by ksz8081mlx register number (hex) description 0h basic control 1h basic status 2h phy identifier 1 3h phy identifier 2 4h auto-negotiation advertisement 5h auto-negotiation link partner ability 6h auto-negotiation expansion 7h auto-negotiation next page 8h link partner next page ability 9h reserved 10h digital reserved control 11h afe control 1 12h - 14h reserved 15h rxer counter 16h operation mode strap override 17h operation mode strap status 18h expanded control 19h - 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd control/status 1eh phy control 1 1fh phy control 2 table 4-2: register descriptions address name description mode note 4-1 default register 0h ? basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.14 loopback 1 = loopback mode 0 = normal operation rw 0 0.13 speed select 1 = 100 mbps 0 = 10 mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1). rw set by the speed strapping pin. see the strap-in options section for details.
? 2016 microchip technology inc. ds00002264a-page 27 ksz8081mlx 0.12 auto-negoti- ation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process if enabled, the auto-negotiation result overrides the settings in registers 0.13 and 0.8. rw set by the nwayen strapping pin. see the strap-in options section for details. 0.11 power-down 1 = power-down mode 0 = normal operation if software reset (register 0.15) is used to exit power-down mode (register 0.11 = 1), two soft- ware reset writes (register 0.15 = 1) are required. the first write clears power-down mode; the sec- ond write resets the chip and re-latches the pin strapping pin values. rw 0 0.10 isolate 1 = electrical isolation of phy from mii 0 = normal operation rw set by the iso strap- ping pin. see the strap-in options section for details. 0.9 restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation. this bit is self-cleared after a ?1? is written to it. rw/sc 0 0.8 duplex mode 1 = full-duplex 0 = half-duplex rw the inverse of the duplex strapping pin value. see the strap-in options section for details. 0.7 collision test 1 = enable col test 0 = disable col test rw 0 0.6:0 reserved reserved ro 000_0000 register 1h - basic status 1.15 100base-t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base-tx full-duplex 1 = capable of 100 mbps full-duplex 0 = not capable of 100 mbps full-duplex ro 1 1.13 100base-tx half-duplex 1 = capable of 100 mbps half-duplex 0 = not capable of 100 mbps half-duplex ro 1 1.12 10base-t full-duplex 1 = capable of 10 mbps full-duplex 0 = not capable of 10 mbps full-duplex ro 1 1.11 10base-t half-duplex 1 = capable of 10 mbps half-duplex 0 = not capable of 10 mbps half-duplex ro 1 1.10:7 reserved reserved ro 000_0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto-negoti- ation com- plete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto-negoti- ation ability 1 = can perform auto-negotiation 0 = cannot perform auto-negotiation ro 1 table 4-2: register descriptions (continued) address name description mode note 4-1 default
ksz8081mlx ds00002264a-page 28 ? 2016 microchip technology inc. 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capability registers ro 1 register 2h - phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organi- zationally unique identif ier (oui). kendin com- munication?s oui is 0010a1 (hex). ro 0022h register 3h - phy identifier 2 3.15:10 phy id num- ber assigned to the 19th through 24th bits of the orga- nizationally unique iden tifier (oui). kendin com- munication?s oui is 0010a1 (hex). ro 0001_01 3.9:4 model num- ber six-bit manufacturer?s model number ro 01_0110 3.3:0 revision number four-bit manufacturer?s revision number ro indicates silicon revision. register 4h - auto-negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability note: recommend to set this bit to ?0?. rw 1 4.14 reserved reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved reserved ro 0 4.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and symmetric pause rw 00 4.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base-tx full-duplex 1 = 100 mbps full-duplex capable 0 = no 100 mbps full-duplex capability rw set by the speed strapping pin. see the strap-in options section for details. 4.7 100base-tx half-duplex 1 = 100 mbps half-duplex capable 0 = no 100 mbps half-duplex capability rw set by the speed strapping pin. see the strap-in options section for details. 4.6 10base-t full-duplex 1 = 10 mbps full-duplex capable 0 = no 10 mbps full-duplex capability rw 1 4.5 10base-t half-duplex 1 = 10 mbps half-duplex capable 0 = no 10 mbps half-duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 table 4-2: register desc riptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002264a-page 29 ksz8081mlx register 5h - auto-negotia tion link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and symmetric pause ro 00 5.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base-tx full-duplex 1 = 100 mbps full-duplex capable 0 = no 100 mbps full-duplex capability ro 0 5.7 100base-tx half-duplex 1 = 100 mbps half-duplex capable 0 = no 100 mbps half-duplex capability ro 0 5.6 10base-t full-duplex 1 = 10 mbps full-duplex capable 0 = no 10 mbps full-duplex capability ro 0 5.5 10base-t half-duplex 1 = 10 mbps half-duplex capable 0 = no 10 mbps half-duplex capability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 0_0001 register 6h - auto-n egotiation expansion 6.15:5 reserved reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capabil- ity ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto-negoti- ation able 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability ro 0 register 7h - auto-n egotiation next page 7.15 next page 1 = additional next pages will follow 0 = last page rw 0 7.14 reserved reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowl- edge2 1 = will comply with message 0 = cannot comply with message rw 0 table 4-2: register descriptions (continued) address name description mode note 4-1 default
ksz8081mlx ds00002264a-page 30 ? 2016 microchip technology inc. 7.11 toggle 1 = previous value of the transmitted link code word equaled logic 1 0 = logic 0 ro 0 7.10:0 message field 11-bit wide field to encode 2048 messages rw 000_0000_0001 register 8h - link partner next page ability 8.15 next page 1 = additional next pages will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful re ceipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowl- edge2 1 = can act on the information 0 = cannot act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic 0 0 = previous value of transmitted link code word equal to logic 1 ro 0 8.10:0 message field 11-bit wide field to encode 2048 messages ro 000_0000_0000 register 10h ? digital reserved control 10.15:5 reserved reserved rw 0000_0000_000 10.4 pll off 1 = turn pll off automatically in edpd mode 0 = keep pll on in edpd mode. see also register 18h, bit [11] for edpd mode rw 0 10.3:0 reserved reserved rw 0000 register 11h ? afe control 1 11.15:6 reserved reserved rw 0000_0000_00 11.5 slow-oscilla- tor mode enable slow-oscillator mode is used to disconnect the input reference crystal/clock on the xi pin and select the on-chip slow oscillator when the ksz8081mlx device is not in use after power-up. 1 = enable 0 = disable this bit automatically sets software power-down to the analog side when enabled. rw 0 11.4:0 reserved reserved rw 0_0000 register 15h ? rxer counter 15.15:0 rxer counter receive error counter for sym bol error frames ro/sc 0000h register 16h ? operation mode strap override 16.15 reserved factory mode 0 = normal operation 1 = factory test mode if txc (pin 33) latches in a pull-up value at the de- assertion of reset, write a ?0? to this bit to clear reserved factory mode. rw 0 set by the pull-up / pull-down value of txc (pin 33). 16.14:11 reserved reserved rw 000_0 16.10 reserved reserved ro 0 table 4-2: register desc riptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002264a-page 31 ksz8081mlx 16.9 b- cast_off override 1 = override strap-in for b-cast_off if bit is ?1?, phy address 0 is non-broadcast. rw 0 16.8 reserved reserved rw 0_0 16.7 mii b-to-b override 1 = override strap-in for mii back-to-back mode (also set bit 1 of this register to ?1?) rw 0 16.6 reserved reserved rw 0 16.5 nand tree override 1 = override strap-in for nand tree mode rw 0 16.4:1 reserved reserved rw 0_000 16.0 mii override 1 = override strap-in for mii mode rw 1 register 17h - operation mode strap status 17.15:13 phyad[2:0] strap-in sta- tus [000] = strap to phy address 0 [001] = strap to phy address 1 [010] = strap to phy address 2 [011] = strap to phy address 3 [100] = strap to phy address 4 [101] = strap to phy address 5 [110] = strap to phy address 6 [111] = strap to phy address 7 ro ? 17.12:10 reserved reserved ro ? 17.9 b- cast_off strap-in status 1 = strap to b-cast_off if bit is ?1?, phy address 0 is non-broadcast. ro ? 17.8 reserved reserved ro ? 17.7 mii b-to-b strap-in status 1 = strap to mii back-to-back mode ro ? 17.6 reserved reserved ro ? 17.5 nand tree strap-in status 1 = strap to nand tree mode ro ? 17.4:1 reserved reserved ro ? 17.0 mii strap-in status 1 = strap to mii mode ro ? register 18h - expanded control 18.15:12 reserved reserved rw 0000 18.11 edpd disabled energy-detect power-down mode 1 = disable 0 = enable see also register 10h, bit [4] for pll off. rw 1 18.10 100base-tx latency 1 = mii output is random latency 0 = mii output is fixed latency for both settings, all bytes of received preamble are passed to the mii output. rw 0 18.9:7 reserved reserved rw 00_0 table 4-2: register descriptions (continued) address name description mode note 4-1 default
ksz8081mlx ds00002264a-page 32 ? 2016 microchip technology inc. 18.6 10base-t preamble restore 1 = restore received preamble to mii output 0 = remove all seven bytes of preamble before sending frame (starting with sfd) to mii output rw 0 18.5:0 reserved reserved rw 00_0000 register 1bh ? interrupt control/status 1b.15 jabber inter- rupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error inter- rupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowl- edge inter- rupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 1b.10 link-down interrupt enable 1= enable link-down interrupt 0 = disable link-down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link-up interrupt enable 1 = enable link-up interrupt 0 = disable link-up interrupt rw 0 1b.7 jabber inter- rupt 1 = jabber occurred 0 = jabber did not occur ro/sc 0 1b.6 receive error inter- rupt 1 = receive error occurred 0 = receive error did not occur ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occur ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occur ro/sc 0 1b.3 link partner acknowl- edge inter- rupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occur ro/sc 0 1b.2 link-down interrupt 1 = link-down occurred 0 = link-down did not occur ro/sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occur ro/sc 0 table 4-2: register desc riptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002264a-page 33 ksz8081mlx 1b.0 link-up interrupt 1 = link-up occurred 0 = link-up did not occur ro/sc 0 register 1dh ? linkmd control/status 1d.15 cable diag- nostic test enable 1 = enable cable diagnostic test. after test has completed, this bit is self-cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 1d.14:13 cable diag- nostic test result [00] = normal condition [01] = open condition has been detected in cable [10] = short condition has been detected in cable [11] = cable diagnostic test has failed ro 00 1d.12 short cable indicator 1 = short cable (<10 meter) has been detected by linkmd ro 0 1d.11:9 reserved reserved rw 000 1d.8:0 cable fault counter distance to fault ro 0_0000_0000 register 1eh ? phy control 1 1e.15:10 reserved reserved ro 0000_00 1e.9 enable pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0 1e.8 link status 1 = link is up 0 = link is down ro 0 1e.7 polarity sta- tus 1 = polarity is reversed 0 = polarity is not reversed ro ? 1e.6 reserved reserved ro 0 1e.5 mdi/mdi-x state 1 = mdi-x 0 = mdi ro ? 1e.4 energy detect 1 = signal present on receive differential pair 0 = no signal detected on receive differential pair ro 0 1e.3 phy isolate 1 = phy in isolate mode 0 = phy in normal operation rw 0 1e.2:0 operation mode indica- tion [000] = still in auto-negotiation [001] = 10base-t half-duplex [010] = 100base-tx half-duplex [011] = reserved [100] = reserved [101] = 10base-t full-duplex [110] = 100base-tx full-duplex [111] = reserved ro 000 register 1fh ? phy control 2 1f.15 hp_mdix 1 = hp auto mdi/mdi-x mode 0 = microchip auto mdi/mdi-x mode rw 1 table 4-2: register descriptions (continued) address name description mode note 4-1 default
ksz8081mlx ds00002264a-page 34 ? 2016 microchip technology inc. note 4-1 rw = read/write; ro = read only; sc = self-cleared; lh = latch high; ll = latch low. 1f.14 mdi/mdi-x select when auto mdi/mdi-x is disabled, 1 = mdi-x mode transmit on rxp, rxm (pins 10, 9) and receive on txp, txm (pins 12, 11) 0 = mdi mode transmit on txp, txm (pins 12, 11) and receive on rxp, rxm (pins 10, 9) rw 0 1f.13 pair swap disable 1 = disable auto mdi/mdi-x 0 = enable auto mdi/mdi-x rw 0 1f.12 reserved reserved rw 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link. rw 0 1f.10 power sav- ing 1 = enable power saving 0 = disable power saving rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable jab- ber 1 = enable jabber counter 0 = disable jabber counter rw 1 1f.7:6 reserved reserved rw 0 1f.5:4 led mode [00] = led1: speed led0: link/activity [01] = led1: activity led0: link [10], [11] = reserved rw 00 1f.3 disable transmitter 1 = disable transmitter 0 = enable transmitter rw 0 1f.2 remote loopback 1 = remote (analog) loopback is enabled 0 = normal mode rw 0 1f.1 enable sqe te s t 1 = enable sqe test 0 = disable sqe test rw 0 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 table 4-2: register desc riptions (continued) address name description mode note 4-1 default
? 2016 microchip technology inc. ds00002264a-page 35 ksz8081mlx 5.0 operational characteristics 5.1 absolute maximum ratings* supply voltage (v in ) (v dd_1.2 ).............................................................................................................................. ...................... ?0.5v to +1.8v (v ddio , v dda_3.3 ) .............................................................................................................................. ........ ?0.5v to +5.0v input voltage (all inputs)..................................................................................................... ....................... ?0.5v to +5.0v output voltage (all outputs)................................................................................................... .................... ?0.5v to +5.0v lead temperature (soldering, 10s) .............................................................................................. ......................... +260c storage temperature (t s ) .............. .............. .............. .............. .............. .............. .............. .............. ...... ?55c to +150c *exceeding the absolute maximum rating may damage the dev ice. stresses greater than the absolute maximum rating may cause permanent damage to the device. operation of the de vice at these or any other conditions above those spec- ified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. 5.2 operating ratings** supply voltage (v ddio_3.3 , v dda_3.3 ) ........................................................................................................................ +3.135 v to +3.465v (v ddio_2.5 ) .............................................................................................................................. .......... +2.375v to +2.625v (v ddio_1.8 ) .............................................................................................................................. .......... +1.710v to +1.890v ambient temperature (t a commercial)................................................................................................................... ........................ 0c to +70c (t a industrial) ........... .............. .............. .............. .............. .............. .............. ........... ......... ........................ ?40c to +85c maximum junction temperature (t j max.) ........................................................................................................... +125c thermal resistance ( ja ).............................................................................................................................. .....+76c/w thermal resistance ( jc ) .............................................................................................................................. ....+15c/w **the device is not guaranteed to function outside its operating ratings. note: do not drive input signals without power supplied to the device.
ksz8081mlx ds00002264a-page 36 ? 2016 microchip technology inc. 6.0 electrical characteristics t a = 25c. specification is for packaged product only. table 6-1: electrical characteristics parameters symbol min. typ. max. units note supply current (v ddio , v dda_3.3 = 3.3v), note 6-1 10base-t i dd1_3.3v ? 41 ? ma full-duplex traffic @ 100% utilization 100base-tx i dd2_3.3v ? 47 ? ma full-duplex traffic @ 100% utilization edpd mode i dd3_3.3v ?20?ma ethernet cable disconnected (reg. 18h.11 = 0) power-down mode i dd4_3.3v ?4?ma software power-down (reg. 0h.11 = 1) cmos level inputs output high voltage v oh 2.4 ? ? v v ddio = 3.3v 2.0 ? ? v v ddio = 2.5v 1.5 ? ? v v ddio = 1.8v output low voltage v ol ??0.4v v ddio = 3.3v ??0.4v v ddio = 2.5v ??0.3v v ddio = 1.8v output tri-state leakage |i oz |??10a ? led output output drive current i led ? 8 ? ma each led pin (led0, led1) all pull-up/pull-down pins (including strapping pins) internal pull-up resistance pu 30 45 73 k ? v ddio = 3.3v 39 61 102 k ? v ddio = 2.5v 48 99 178 k ? v ddio = 1.8v internal pull-down resistance pd 26 43 79 k ? v ddio = 3.3v 34 59 113 k ? v ddio = 2.5v 53 99 200 k ? v ddio = 1.8v 100base-tx transmit (measured differentially after 1:1 transformer) peak differential output voltage v o 0.95 ? 1.05 v 100 ? termination across differential output output voltage imbalance v imb ?? 2 % 100 ? termination across differential output rise/fall time t r /t f 3?5ns ? rise/fall time imbalance ? 0 ? 0.5 ns ? duty cycle distortion ? ? ? 0.25 ns ? overshoot ? ? ? 5 % ? output jitter ? ? 0.7 ? ns peak-to-peak 10base-t transmit (measured differentially after 1:1 transformer) peak differential output voltage v p 2.2 ? 2.8 v 100 ? termination across differential output jitter added ? ? ? 3.5 ns peak-to-peak rise/fall time t r /t f ?25?ns ? 10base-t receive squelch threshold v sq ? 400 ? mv 5 mhz square wave transmitter - drive setting reference voltage of i set v set ?0.65? v r(i set ) = 6.49 k ?
? 2016 microchip technology inc. ds00002264a-page 37 ksz8081mlx note 6-1 current consumption is for t he single 3.3v supply ksz8081mlx device only, and includes the transmit driver current and the 1.2v supply voltage (v dd_1.2 ) that are supplied by the ksz8081mlx. 100 mbps mode - industrial applications parameters clock phase delay ? xi input to mii txc output ? 152025ns xi (25 mhz clock input) to mii txc (25 mhz clock outp ut) delay, refer- enced to rising e dges of both clocks. link loss reaction (indication) time t llr ?4.4? s link loss detected at receive differential inputs to phy signal indication time for each of the following: 1. for led mode 01, link led output changes from low (link-up) to high (link-down). 2. intrp pin asserts for link-down status change. table 6-1: electrical characteristics (continued) parameters symbol min. typ. max. units note
ksz8081mlx ds00002264a-page 38 ? 2016 microchip technology inc. 7.0 timing diagrams 7.1 mii sqe timing (10base-t) figure 7-1: mii sqe timing (10base-t) table 7-1: mii sqe timing (10base-t) parameters parameter description min. typ. max. units t p txc period ? 400 ? ns t wl txc pulse width low ? 200 ? ns t wh txc pulse width high ? 200 ? ns t sqe col (sqe) delay after txen de-asserted ? 2.2 ? s t sqep col (sqe) pulse duration ? 1.0 ? s t wl t wh t p t sqe t sqep txc txen col
? 2016 microchip technology inc. ds00002264a-page 39 ksz8081mlx 7.2 mii transmit timing (10base-t) figure 7-2: mii transm it timing (10base-t) table 7-2: mii transmit timing (10base-t) parameters parameter description min. typ. max. units t p txc period ? 400 ? ns t wl txc pulse width low ? 200 ? ns t wh txc pulse width high ? 200 ? ns t su1 txd[3:0] setup to rising edge of txc 120 ? ? ns t su2 txen setup to rising edge of txc 120 ? ? ns t hd1 txd[3:0] hold from rising edge of txc 0 ? ? ns t hd2 txen hold from rising edge of txc 0 ? ? ns t crs1 txen high to crs asserted latency ? 600 ? ns t crs2 txen low to crs de-asserted latency ? 1.0 ? s crs txen txd[3:0] txc t crs1 t wl t p t hd2 t crs2 t wh t hd1 t su2 t su1
ksz8081mlx ds00002264a-page 40 ? 2016 microchip technology inc. 7.3 mii receive timing (10base-t) figure 7-3: mii receive timing (10base-t) table 7-3: mii receive timing (10base-t) parameters parameter description min. typ. max. units t p rxc period ? 400 ? ns t wl rxc pulse width low ? 200 ? ns t wh rxc pulse width high ? 200 ? ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc ?205? ns t rlat crs to (rxdv, rxd[ 3:0]) latency ? 7.2 ? s crs rxdv rxd[3:0] rxer rxc t rlat t od t p t wl t wh
? 2016 microchip technology inc. ds00002264a-page 41 ksz8081mlx 7.4 mii transmit timing (100base-tx) figure 7-4: mii transmit timing (100base-tx) table 7-4: mii transmit timing (100base-tx) parameters parameter description min. typ. max. units t p txc period ? 40 ? ns t wl txc pulse width low ? 20 ? ns t wh txc pulse width high ? 20 ? ns t su1 txd[3:0] setup to rising edge of txc 10 ? ? ns t su2 txen setup to rising edge of txc 10 ? ? ns t hd1 txd[3:0] hold from rising edge of txc 0 ? ? ns t hd2 txen hold from rising edge of txc 0 ? ? ns t crs1 txen high to crs asserted latency ? 72 ? ns t crs2 txen low to crs de-asserted latency ? 72 ? ns crs txen txd[3:0] txc t crs1 t wl t p t hd1 t su1 t crs2 data in t wh t hd2 t su2
ksz8081mlx ds00002264a-page 42 ? 2016 microchip technology inc. 7.5 mii receive timing (100base-tx) figure 7-5: mii receive timing (100base-tx) table 7-5: mii receive timing (10base-t) parameters parameter description min. typ. max. units t p rxc period ? 40 ? ns t wl rxc pulse width low ? 20 ? ns t wh rxc pulse width high ? 20 ? ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 16 21 25 ns t rlat crs to (rxdv, rxd[3:0]) latency ? 170 ? ns crs rxdv rxd[3:0] rxer rxc t rlat t od t p t wl t wh
? 2016 microchip technology inc. ds00002264a-page 43 ksz8081mlx 7.6 auto-negotiation timing figure 7-6: auto-negotiation fast link pulse (flp) timing table 7-6: auto-negotiation fast link pulse timing parameters parameter description min. typ. max. units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width ? 2 ? ms t pw clock/data pulse width ? 100 ? ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s ? number of clock/data pulses per flp burst 17 ? 33 ? auto -negotiation fast link pulse (flp) timing t pw tx+/tx- clock pulse data pulse clock pulse t pw t ctd t ctc t flpw t btb tx+/tx- data pulse flp burst flp burst
ksz8081mlx ds00002264a-page 44 ? 2016 microchip technology inc. 7.7 mdc/mdio timing figure 7-7: mdc/mdio timing table 7-7: mdc/mdio timing parameters parameter description min. typ. max. units f c mdc clock frequency ? 2.5 10 mhz t p mdc period ? 400 ? ns t md1 mdio (phy input) setup to rising edge of mdc 10 ? ? ns t md2 mdio (phy input) hold from rising edge of mdc 4 ? ? ns t md3 mdio (phy output) delay from rising edge of mdc 5 222 ? ns t md1 valid data mdio (phy input) valid data mdc t md2 mdio (phy output) valid data t md3 t p
? 2016 microchip technology inc. ds00002264a-page 45 ksz8081mlx 7.8 power-up/reset timing the ksz8081mlx reset timing requirement is summarized in figure 7-8 and ta b l e 7 - 8 . the supply voltage (v ddio and v dda_3.3 ) power-up waveform should be monotonic. the 300 s minimum rise time is from 10% to 90%. for warm reset, the reset (rst#) pin should be asserted low for a minimum of 500 s. the strap-in pin values are read and updated at the de-assertion of reset. after the de-assertion of reset, wait a minimum of 100 s before starting programming on the miim (mdc/mdio) inter- face. figure 7-8: power-up/reset timing table 7-8: power-up/reset timing parameters parameter description min. typ. max. units t vr supply voltage (v ddio , v dda_3.3 ) rise time 300 ? ? s t sr stable supply voltage (v ddio , v dda_3.3 ) to reset high 10 ? ? ms t cs configuration setup time 5 ? ? ns t ch configuration hold time 5 ? ? ns t rc reset to strap-in pin output 6 ? ? ns supply voltages rst# strap-in value strap-in / output pin t vr t sr t cs t ch t rc
ksz8081mlx ds00002264a-page 46 ? 2016 microchip technology inc. 8.0 reset circuit figure 8-1 shows a reset circuit recommended for powering up the ksz8081mlx if reset is triggered by the power sup- ply. figure 8-1: recommended reset circuit figure 8-2 shows a reset circuit recommended for applications w here reset is driven by another device (for example, the cpu or an fpga). the reset out rst_out_n from cp u/fpga provides the warm reset after power up reset. d2 is used if using different v ddio between the switch and cpu/fp ga, otherwise, the different v ddio will fight each other. if different v ddio have to use in a special case, a low v f (<0.3v) diode is required (for example, vishay?s bat54, mss1p2l and so on), or a level shifter device can be us ed too. if ethernet device and cpu/fpga use same v ddio voltage, d2 can be removed to connect both devices dire ctly. usually, ethernet device and cpu/fpga should use same v ddio voltage. figure 8-2: recommended reset cir cuit for cpu/fpga reset output vddio d1: 1n4148 d1 r 10k ksz8081mlx rst# c 10f vddio ksz8081mlx d1 r 10k rst# c 10f d2 cpu/fpga rst_out_n d1, d2: 1n4148
? 2016 microchip technology inc. ds00002264a-page 47 ksz8081mlx 9.0 reference circuits ? led strap-in pins the pull-up, float, and pull-down reference circuits for the led0/nwayen strapping pin are shown in figure 9-1 for 3.3v and 2.5v v ddio . figure 9-1: reference circuits for led strapping pins for 1.8v v ddio , led indication support is not recommended due to the low voltage. without the led indicator, the speed and nwayen strap-in pins are functional with a 4.7 k ? pull-up to 1.8v v ddio or float for a value of ?1?, and with a 1.0 k ? pull-down to ground for a value of ?0?. if using rj45 jacks with int egrated leds and 1.8v v ddio , a level shifting is required from led 3.3v to 1.8v. for example, use a bipolar transistor or a level shift device. led pin 220 ? 4.7k ? pull-up ksz8081mlx vddio = 3.3v, 2.5v led pin 220 ? float ksz8081mlx vddio = 3.3v, 2.5v led pin 220 ? pull-down ksz8081mlx vddio = 3.3v, 2.5v 1k ?
ksz8081mlx ds00002264a-page 48 ? 2016 microchip technology inc. 10.0 reference clock - connection and selection a crystal or external clock source, such as an oscillator, is used to provide the reference clock for the ksz8081mlx. for the ksz8081mlx in all operating modes, the reference clock is 25 mhz. the reference clock connections to xi (pin 15) and xo (pin 14), and the reference cl ock selection criteria, are provided in figure 10-1 and table 10-1 . figure 10-1: 25 mhz crystal/oscillator reference clock connection note 10-1 60 ppm for overtemperature crystal. table 10-1: 25 mhz crystal/refer ence clock selec tion criteria characteristics value frequency 25 mhz frequency tolerance (max.); note 10-1 50 ppm crystal series resistance (typ.) 40 ? crystal load capacitance (typ.) 16 pf nc xi xo 25mhz osc 50ppm xi xo 25mhz xtal 50ppm 22pf 22pf
? 2016 microchip technology inc. ds00002264a-page 49 ksz8081mlx 11.0 magnetic - connec tion and selection a 1:1 isolation transformer is required at the line interfac e. use one with integrated common-mode chokes for designs exceeding fcc requirements. the ksz8081mlx design incorporates voltage-mode transmit drivers and on-chip terminations. with the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential pairs. therefore, the two transformer center tap pins on the ksz8081mlx side should not be connected to any power supply source on the board; instead, t he center tap pins should be separate d from one another and connected through separate 0.1 f common-mode capacitors to ground. separa tion is required because the common-mode voltage is dif- ferent between transmitting and receiving differential pairs. figure 11-1 shows the typical magnetic interface circuit for the ksz8081mlx. figure 11-1: typical magnetic interface circuit table 11-1 lists recommended magnetic characteristics. table 11-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the phy chip side that can be used with the ksz8081mlx. table 11-1: magnetics selection criteria parameter value test conditions turns ratio 1 ct : 1 ct ? open-circuit inductance (min.) 350 h 100 mv, 100 khz, 8 ma insertion loss (max.) ?1.1 db 100 khz to 100 mhz hipot (min.) 1500 v rms ? 1 2 3 7 8 4 5 6 4 x 75 ? 1000pf/2kv rj-45 connector chassis ground (2 x 0.1f) txp txm rxp rxm ksz8081rna/rnd signal ground
ksz8081mlx ds00002264a-page 50 ? 2016 microchip technology inc. table 11-2: compatible sing le-port 10/100 magnetics manufacturer part number temperature range magnetic + rj-45 bel fuse s558-5999-u7 0c to 70c no bel fuse si-46001-f 0c to 70c yes bel fuse si-50170-f 0c to 70c yes delta lf8505 0c to 70c no halo hfj11-2450e 0c to 70c yes halo tg110-e055n5 ?40c to 85c no lankom lf-h41s-1 0c to 70c no pulse h1102 0c to 70c no pulse h1260 0c to 70c no pulse hx1188 ?40c to 85c no pulse j00-0014 0c to 70c yes pulse jx0011d21nl ?40c to 85c yes tdk tla-6t718a 0c to 70c yes transpower hb726 0c to 70c no wurth/midcom 000-7090-37r-lf1 ?40c to 85c no
? 2016 microchip technology inc. ds00002264a-page 51 ksz8081mlx 12.0 package outline figure 12-1: 48-lead lqfp 7 mm x 7 mm package note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging.
ksz8081mlx ds00002264a-page 52 ? 2016 microchip technology inc. appendix a: data sheet revision history table a-1: revision history revision section/figure/entry correction ds00002264a (08-30-16) ? converted micrel data sheet ksz8081mlx to microchip ds00002264a. minor text changes throughout.
? 2016 microchip technology inc. ds00002264a-page 53 ksz8081mlx the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site con- tains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), te chnical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of semi- nars and events, listings of microchip sales offi ces, distributors and factory representatives customer change notification service microchip?s customer notification servic e helps keep customers current on microc hip products. subscribers will receive e-mail notification whenever there are changes, updates, revisi ons or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notifi- cation? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this docu- ment. technical support is available through the web site at: http://microchip.com/support
ksz8081mlx ds00002264a-page 54 ? 2016 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or de livery, refer to the factory or the listed sales office . device: ksz8081 interface: m = mii package: l = 48-pin lqfp special attribute: x = none temperature: ca = 0 ? c to +70 ? c (commercial) ia = ?40 ? c to +85 ? c (industrial) media type: blank = tray tr = tape & reel examples: a) ksz8081mlxca mii interface 48-pin lqfp no special attribute commercial temperature tray b) ksz8081mlxia mii interface 48-pin qfn no special attribute industrial temperature tray c) ksz8081mlxca-tr mii interface 48-pin qfn no special attribute commercial temperature tape & reel d) KSZ8081MLXIA-TR mii interface 48-pin qfn no special attribute industrial temperature tape & reel part no. x x package interface device xx temperature x special attribute xx media type
? 2016 microchip technology inc. ds00002264a-page 55 information contained in this publication regarding device applications and the like is provided on ly for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with yo ur specifications. microchip make s no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fi tness for purpose . microchip disclaims all liability arising from this information and its use. use of micro- chip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemn ify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, impl icitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip l ogo, anyrate, dspic, flashflex, flexpw r, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersyn ch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered tradem arks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, body com, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit se rial programming, icsp, inter-c hip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, re al ice, ripple blocker, serial quad i/o, sqi, superswitcher, super switcher ii, total endurance, ts harc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of mi crochip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchi p technology incorporated in the u.s.a. silicon storage technology is a regi stered trademark of microchip tech nology inc. in other countries. gestic is a registered trademarks of microc hip technology germany ii gmbh & co. kg, a s ubsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0908-3 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development syst ems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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